The development of backside optical probing techniques for integrated circuits was initially driven by the adoption of flipchip packaging. Since flipchip devices are mounted with the top surface of die in contact with package, visual access is typically limited to the backside of the die.
Optical waveform probing for timing analysis, and failsite isolation techniques such as Photon Emission Microscopy (PEM), Optical Beam Induced Current (OBIC), Light Induced Voltage Alteration (LIVA), Thermally Induced Voltage Alteration (TIVA), Schlieren Thermal Mapping (STM), Fluorescence Microthermal Imaging (FMI), may be applied to the backside of an integrated circuit.
Although many optical probing techniques were initially developed with flipchip devices in mind, the increased complexity and density of interconnect layers of non-flipchip devices have made backside optical probing desirable for non-flipchip devices as well.
In contrast to flipchip devices in which the backside is generally accessible, packaged non-flipchip devices require partial removal of the package to obtain access to the backside of the die. It is also advantageous to reduce the thickness of the die.
Prior Art FIG. 1A shows a cross-section view 100 of a conventionally packaged integrated circuit die 125. The integrated circuit die 125 is mounted on a heat sink/base 105 that is attached to a frame 110. A trace 115 is embedded in the frame 110 and provides a signal path between a ball 120 and a wirebond 130. An encapsulant (e.g., epoxy) 145 covers the die 125.
With respect to the packaged integrated circuit 100, there are four principal surfaces (or planes) of concern: the die mounting surface 106, the package bottom surface 107, the package wirebonding surface 135 and the die top surface 140. The relationship between the four surfaces is generally determined by circuit performance and assembly requirements. Ease of modification for optical probing or other backside operations has not been a primary consideration.
Prior Art FIG. 1B shows a cross-section view 101 of the packaged integrated circuit of FIG. 1A after thinning. The thinned packaged integrated circuit has the heat sink removed (e.g., by lapping) to expose the die 125, with the encapsulant 145 providing mechanical support.
The conventional package of FIG. 1B has the disadvantage of an inherent minimum thickness Tmin for the thinned die 125. Tmin is approximately the difference in height between the die top surface 140 and the package wirebonding surface 135. Thinning below Tmin will result in the removal of trace 115 and an open circuit.
Another disadvantage is the effort required to remove heat sink 105, and thin frame 110. For mechanical thinning operations such as lapping or polishing the presence of the frame 110 may degrade the quality of the surface finish obtained on the die 110. Due to the difference in properties between the die 125 and the heat sink 105, two distinct lapping processes are typically required. The time required for lapping is also increased due to the additional material that must be removed.
Prior Art FIG. 1C shows a cross-section view 102 of a conventional pin grid array (PGA) package with a semiconductor die 125. The PGA package includes a base 150 that supports a trace 155 that connects a wirebond 160 to a pin 165. The base 150 has a mounting region 160 for supporting the semiconductor die 125.
Alternatively specialized tools are used to remove only the section of heat sink below the semiconductor die. While this reduces the minimum thickness Tmin, it has a number of limitations. The most significant of these is the cavity that is created. Optical probing typically requires a wide (e.g., 1 inch) lens to sit very near, or in contact with, the thinned substrate. This means that the lens must be used inside the cavity, which limits its lateral movement. In turn, the full die is no longer visible.